Tamper targets are regions of software used to configure hardware logic devices (e.g., Field-programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), etc.) that are susceptible to vulnerabilities. A vulnerability can comprise instructions that lead to the hardware logic devices operating in an undesired manner (or failure of the hardware logic devices). Additionally, a vulnerability can comprise instructions that result in a trojan being inserted into hardware (referred to as a trojan insertion). The vulnerabilities are often detected only after the hardware logic devices have been field-operated. Further, detecting vulnerabilities is difficult because conventional hardware logic devices comprise inordinately large numbers of possible activation mechanisms for the vulnerabilities.
Untrusted design tools can place a trojan insertion in the software during the design of a hardware logic device. A trojan insertion can act as a “spy” for actors responsible for the trojan insertion or lead to failure of a hardware logic device that has been subject to the trojan insertion. Further, a trojan insertion can be designed such that the resultant trojan remains hidden for normal operation and conventional testing of the hardware logic device.
At hardware logic device design and verification stages, hardware logic device software can be considered trusted due to being managed by trusted operators. Trust via chain-of-custody, however, breaks down because the untrusted design tools can insert trojans into the hardware logic device software (e.g., netlists) at stages of the hardware logic device design that are not verified at verification stages. There are currently no scalable or diverse means of ensuring that hardware logic devices are trustworthy based upon the trusted stages of hardware logic design and verification.